The invention relates to a power-on method for a computer system, and in particular, to a method of initializing a computer system comprising a processor supporting hyper-threading
FIG. 1 shows a conventional computer system diagram. The computer system 100 comprises a processor 102, Northbridge 104, main memory 106, Southbridge 108 and ROM 110. The processor 102 comprises a cache memory 112. The ROM 110 comprises BIOS codes for initialization of the components in the computer system 100, such as main memory refresh cycle and clock frequency. When the computer system 100 is powered on, a Power On Self Test (POST) is processed, and BIOS codes stored in the ROM 110 are executed by the Northbridge 104 and Southbridge 108 for system calibration and activation. Simultaneously, the main memory 106 is initialized by the processor 102 based on the instructions in the BIOS codes stored in the ROM 110. Conventionally, the initialization of main memory 106 comprises a plurality of complex procedures such as read/write tests, thereby corresponding results are stored in the registers of Northbridge 104 for system operation. As shown in route 2, cache memory 112 is utilized to store a copy of the BIOS codes, and the results of read/write tests. Route 3 shows that the processor 102 directly executes the BIOS codes in the cache memory 112 to initialize the main memory 106 and program the Northbridge 104. The performance is improved because the speed of cache memory 112 is much faster than ROM 110.
The described power-on method, however, is not adaptable for processors supporting Hyper-Threading technologies. A Hyper-Threading processor comprising two logic units, only activates the first logic unit by default at power-on. A specific initialization procedure is required to activate the second logic unit, and the Hyper-Threading processor is not fully operational until a supported operating system is loaded. The initialization procedure for the second logic unit requires help of the main memory 106 that requires the cache memory 112 to initialize, as shown in Route 2 and 3 in FIG. 1. By default, before the second logic unit is initialized, the cache memory 112 is in a mode referred to as “No-Fill Cache” that is not usable due to the disorder of write back address allocation. As a result, a deadlock occurs.